报告时间：2017年10月10号早上9:30-11:30

报告地点：数计学院4号楼229 （第一报告厅）

Title:

Timing is Everything…

Speaker:

Iris Hui-Ru Jiang

Graduate Institute of Electronics Engineering

Department of Electrical Engineering

National Taiwan University

Abstract:

In this talk, we investigate several key issues that should be handled by timing analysis tools for facilitating design closure for modern IC designs: common path pessimism removal, incremental timing analysis, and timing macro modeling. Recent research advances on these topics and future directions will be discussed in this talk.

Bio:

Iris Hui-Ru Jiang received the B.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1995 and 2002, respectively. She is currently a Professor with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University and has been a visiting scholar of IBM Austin Research Laboratory from 2013 to 2014. Her current research interests include interaction between logic design and physical synthesis, timing analysis and optimization, physical design optimization, design for manufacturability, and data analytics based design automation.

Dr. Jiang received Best Paper Award Nomination from DAC 2016 and ISPD 2013 and Best in-track Paper from ICCAD 2014. She and her students was the recipient of the First Place Award at the CAD Contest at ICCAD in 2012. Her group has received Awards at the TAU Timing Analysis Contests (5 years in a row since 2013). She was the recipient of the 2011 Chinese Institute of Electrical Engineering Outstanding Young Electrical Engineer Award. She is currently the chair of IEEE CEDA Design Automation Technical Committee (DATC), and organized CAD contest at ICCAD from 2012 to 2014 and CADathlon@ICCAD since 2016. She is currently an associate editor of IEEE TCAD and has served on technical program committees of major EDA conferences, including DAC, ICCAD, ISPD, ASP-DAC, SLIP, and IWLS.