Talk :On Placing Heterogeneous FPGAs

报告时间：2016年12月2号，10am-11:00am

报告地点：数计学院4号楼第1报告厅

Abstract:

Packing and Placement are two crucial stages for FPGA implement. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are clustered in the packing stage has a great impact on the placement quality. This talk presents an analytical placement framework for heterogeneous FPGAs through a rough-placed packing algorithm. Other related techniques for VLSI placement will also be mentioned.

Speaker Bio:

Hung-Ming Chen received the B.S. degree in computer science and information engineering from National Chiao Tung University, Hsinchu, Taiwan, and the M.S. and the Ph.D. degrees in computer sciences from University of Texas at Austin, USA.

Dr. Chen is currently a Professor in the Department of Electronics Engineering at National Chiao Tung University, Hsinchu, Taiwan. He has served as the technical program committee members including ACM/IEEE ASP-DAC, IEEE/ACM ICCADand ACM ISPD. He also served as EDA track co-chair in IEEE VLSI-DAT since 2015. He has supervised a team to win the first place at 2014 ISPD Placement Contest. His research interests include physical design automation in digital and analog circuits,beyond-die integration (off-chip EDA), and design methodologies.